{
  "url": "https://fahrplan.events.ccc.de/rc3/2020/Fahrplan/events/11384.html",
  "id": 11384,
  "guid": "08dd87aa-0226-4461-9877-e8542dc64a33",
  "logo": "/system/events/logos/000/011/384/large/Electronic_component_ttl.jpg?1605367084",
  "date": "2020-12-29T18:00:00+01:00",
  "start": "18:00",
  "duration": "00:40",
  "room": "rC2",
  "slug": "rc3-11384-unconventional_hdl_synthesis_experiments",
  "title": "Unconventional HDL synthesis experiments",
  "subtitle": "Will it synthesize?",
  "track": "Hardware & Making",
  "type": "Talk",
  "language": "en",
  "abstract": "Most synthesis goes from hardware description languages to FPGA bitstreams or ASIC designs, but what else can you do? In this talk I will demonstrate some more unconventional flows to inspire you about all the amazing experiments that are enabled by open source tools!",
  "description": "After a short intro about the open source FPGA ecosystem, I will introduce a project by Dan Ravensloft and myself that synthesizes HDL to 74xx logic chips. Then I will cover a project of mine that synthesizes spreadsheets to HDL. And from there to 74xx logic???",
  "recording_license": "",
  "do_not_record": false,
  "persons": [
    {
      "id": 11827,
      "public_name": "Pepijn de Vos"
    }
  ],
  "links": [
    {
      "url": "https://github.com/Ravenslofty/74xx-liberty",
      "title": "74xx-liberty"
    },
    {
      "url": "https://github.com/pepijndevos/excellerate/",
      "title": "Exellerate"
    }
  ],
  "attachments": [],
  "room_id": "32b5ad05-ab7d-44eb-a6e6-7ca616eed34a",
  "origin": null
}